Research Maze

The Lab for Secure & Intelligent NanoComputing

Director: Prof. Danella Zhao
Current Students
  • Bryan Perez (Ph.D. Student)
  • Noah Jennings (Ph.D. Student)
  • Robert Slick (Ph.D. Student)
  • Zhuoran Li (Ph.D. Student)
  • Evan Savaria (Ph.D. Student)
  • Sabbir Ahmed Khan (Ph.D. Student)
Screen Shot 2021-08-08 at 7.12.40 AMFormer Students
— PhDs —
  • Tung Thanh Le, Nov. 2018, Dissertation: Optimizing Network-on-Chip Designs for Heterogeneous Many-Core Architectures. Employment: J.D. Power.
  • Mingmin Bai. Oct. 2018, Dissertation: Performance-Driven Hierarchical Design and Management of Network-on-Chip in Many-Core System. Employment: Yahoo.
  • Md Farhadur Reza, Aug. 2017, Dissertation: Computation and Communication Optimization in Many-Core Heterogeneous Server-on-Chip". Employment: Assistant Professor, Dept. of Computer Science & Software Engineering, Univ. of Central Missouri.
  • Ruizhe Wu, Ph.D., Dec. 2013, Dissertation Title: Performance-Driven Communication Architecture Design in Irregular, Overlaid and Hybrid Mesh Wireless NoC. Employment: Facebook.
  • Unni Chandran, Ph.D., Aug. 2012, Dissertation Title: Secure and Architectural Design Exploration for Testing of 2D/3D SoCs. Employment: Intel Corp.
  • Yi Wang, Ph.D., June 2010, Dissertation Title: Design of Wireless Network-on-Chip for Improving Communication Performance of Many-Core SoCs. Employment: Xilinx Inc.
— Masters —
  • Bryan Perez, Master, 2020, stay for Ph.D.
  • Evan Pierre Savaria, Master, 2019, stay for Ph.D.
  • John Ashley, Master, 2017.
  • Amin Rezaei, Master, 2016, Ph.D @Northwestern Univ.
  • Ali Khayat Baheri Irani, Master, 2015, Ph.D @UNC Charlotte.
  • Md Farhadur Reza, Master, 2014, stay for Ph.D.
  • Zhe Cui, Master, 2011, Employment: InnoGrit Corp.
  • Ruochi Zhang, Master, 2011, Employment: Apple.
  • Ran Zhang, Master, 2010, Employment: Baidu USA.
  • Ronghua Huang, Master, 2009, Employment: VT iDirect.
  • Ruben Loganantharaj, Master, 2009, Employment: Hewlett Packard Enterprise.
  • Unni Chandran, Master, 2008, stay for Ph.D.

Selected Research Projects

Dr. Zhao and her team's research is currently sponsored by NSF, NSA, ONR, DOD, and CCI.

Tangram: Scaling into the Exascale Era with Reconfigurable Aggregated Virtual Chips — Funded by NSF CCF

The design of general-purpose processors is reaching a performance bottleneck due to the limitations in technology scaling. Chiplet-based systems offer a promising solution by integrating small dies (chiplets) inside one package. On one hand, chiplets enable heterogeneous integration of discrete chip architectures, such as CPUs, GPUs, DSPs, and FPGAs. On the other hand, the design of high-performance chiplet-based systems faces serious challenges: inter-chiplet communication is a critical bottleneck; resource needs to be efficiently shared among the chiplets to improve the performance-cost ratio; power and thermal management need to be optimized for better in-package integration. Consequently, such designs need to take a more holistic approach, and investigations are needed on the cross-cutting issues across the processing nodes, storage and interconnection fabric. This research proposes to build "virtual chips" from heterogeneous aggregated chiplets, so that the system can not only reap the performance benefit of a monolithic super chip but also break the scalability bottleneck. A major outcome of the project will be a set of optimization methods that enable the design of a reconfigurable architecture, leveraging a hybrid wireless interconnect technology to seamlessly connect the computing and memory components.

Securing IoT Devices through Power Side Channel Auditing and Privacy Preserved Convolutional Neural Networks — Funded by CCI

Internet of Things (IoT) devices have become the new cybercrime intermediaries to process cyber attacks and deploy malicious contents. The reasons are two folds. First, the popularity of IoT devices has attracted cybercriminals to conduct large-scale cyber attacks. Second, the cybercriminals also take advantage of the innocence of IoT devices, compared to the dedicated hosts, to deploy cyber attacks and evade the IP blacklist-based detection. Further, some of the IoT devices, such as web cameras and routers, were known for their weak security protection. Although there have been indications of IoT devices misuse, identifying and understanding how such devices are abused are challenging, because IoT bot attacks are stealthy, IoT devices are diverse and resource limited, and desired IoT bot detections need to be non-invasive. As a result, existing techniques cannot be directly applied to capture IoT bots, because they require invasive devices upgrade or modification. Also, these techniques are typically limited to detecting homogeneous devices (e.g., PCs). In this project, a novel scheme is proposed to exploit IoT devices’ power side channel information to identify the compromised IoT devices. Specifically, a universal Smart Plug design is proposed to provide power for heterogeneous IoT devices while at the same time detect malicious bot behaviors through Convolutional Neural Networks (CNN). A real-time detection framework is proposed to offload CNN computation from IoT devices to the cloud while at the same time ensuring data privacy of IoT devices.

DeepPOSE: Securing Transportation systems from GPS Spoofing Attacks — Funded by CCI

Today the Global Positioning System (GPS) service is widely used in our daily lives. Smartphones, wearable devices, aircrafts, unmanned aerial vehicles (UAVs), self-driving cars or autonomous vehicles all rely on GPS to benefit from location based services, e.g., navigation, truck/vehicle monitoring, reporting self location in emergency or for rescue, searching nearby gas stations, restaurants, hotels, etc. While GPS becomes an indispensable element in our daily lives, it is rather vulnerable to GPS spoofing attacks even by low-cost hardware, resulting in potentially life-threatening impact. While there has been a long history of studying GPS spoofing, previous solutions to detect GPS spoofing were either applicable to limited scenarios only, or not effective to smart attackers. Furthermore, new challenges, such as varying attack surfaces and lack of mitigation techniques, make the problem even more challenging today. In this project, a holistic framework, dubbed DeepPOSE is proposed to utilize multimodal sensor data to detect and mitigate GPS spoofing attacks to transportation systems, using Deep Learning technologies and emerging wireless communication techniques.

Sensor Degradation Detection Algorithm for Automated Driving Systems — Funded by CCI

The project will develop a sensor degradation detection algorithm for Automated Driving Systems (ADS). Sources of degraded sensor information include weather, cyberattacks (e.g., direct communication and passive false signage), and sensor malfunction. Incorrect information from a sensor could result in significant safety issues, such as leading the vehicle off the road or causing the vehicle to suddenly stop in the middle of an intersection. A virtual framework will be used to test degraded sensor states and the response of the vehicle control systems to develop the detection algorithm. The framework will integrate the sensors models, environments, vehicle model, cyberattacks, and algorithm. Various events related to sensor perception will be extracted to establish baseline sensor performance and performance metrics using the selected events will be determined for comparison in simulation. Various sensor models, such as GPS, LiDAR and radar will be developed for performance deviation detection simulation. The sensor degradation detection algorithm will aid ADS vehicles in decision making by identifying degraded sensor performance.

Wireless Network-on-Chip: A New Communication Paradigm for Heterogeneous Gigascale MPSoCs — Funded by NSF Career

Many-core System-on-Chip (MCSoC) designs are rapidly emerging, where hundreds or even thousands of IP cores are integrated on a single die. Such MCSoC devices allow superior performance gains while side-stepping the power and heat dissipation limitations of clock frequency scaling. Consequently, the on-chip communication fabric becomes the performance determinant. This project aims at developing a new on-chip communication system, dubbed Wireless Network-on-Chip (WNoC) to sustain the exponential growth of computing performance in the next generation gigascale heterogeneous MCSoCs. The PI lays out the research directions of WNoC from various crucial aspects. The UWB physical layer will be explored to accomplish high data-rate, high bandwidth and low-power wireless on-chip communication. The system architecture will be designed in a way that decouples communication from computation, and a reconfigurable RF infrastructure will be developed to address the heterogeneity of MCSoC. The layered protocol will be specially designed to tackle distinct features of WNoC from conventional wireless networks and to simplify the hardware implementation. Highly compact and configurable RF nodes will be designed to support heterogeneous architecture and customization for specific application mapping. A suite of development and prototyping activities will be carried out to demonstrate the applicability and feasibility of WNoC. Some breakthroughs could be forthcoming in the area of intra-chip RF/wireless interconnect network for high performance computing in the upcoming nanoscale MCSoC paradigm.

A Wireless Nanonetworks Integration and Emulation System for Multi-Processor SoC Research and Education — Funded by NSF MRI

Aiming at establishment of an ultra wideband Radio Frequency Integrated Circuits (RFIC) design flow for the development and testing of RF nodes, this project develops a wireless nanonetworks integration and emulation system. A new on-chip communication system, Wireless Network-on-Chip (WNoC) is proposed using CMOS Ultra WideBand (UWB) intrachip wireless technology to bridge the gap between computation requirements of ubiquitous applications and communication efficiency faced by gigascale MultiProcessor Systems on Chips (MPSoC). The system will support research on developing and prototyping self-configurable, on-chip wireless interconnects for the next generation high-performance and low-power MPSoC. An integrated UWB RFIC design flow will be set for the development of RF nodes, laying the basis for WNoC. The corresponding RF node test and measurement environment will be linked to the implementation process for performance characterization and evaluation. The overall WNoC is demonstrated on a Xilinx FPGS emulation system that enables accurate evaluation of performance, power and area cost, and various design tradeoffs. The application-specific WNoC prototypes is developed to address the challenges associated with this new design paradigm and assess the potential of the WNoC technology. Some breakthroughs could be forthcoming in the area of intra-chip interconnect network for high performance computing in the upcoming nanoscale MPSoC paradigm, hopefully demonstrating the feasibility and applicability of RF/wireless interconnects, and providing cost effective extendable solutions to interconnect and IC designs.